/*******************************************************************************
 *
 * Copyright (c) 2004-2008 by Vivante Corp.  All rights reserved.
 *
 * The material in this file is confidential and contains trade secrets of
 * Vivante Corporation.  This is proprietary information owned by Vivante
 * Corporation.  No part of this work may be disclosed, reproduced, copied,
 * transmitted, or used in any way for any purpose, without the express
 * written permission of Vivante Corporation.
 *
 ******************************************************************************/

/*******************************************************************************
 *
 * This file is automatically generated on Mon Apr 13 01:22:32 2009
 *
 * Any changes made to this file are lost at the next compile run!
 * So better make sure you update the source .r files instead!
 *
 ******************************************************************************/

////////////////////////////////////////////////////////////////////////////////
//                             ~~~~~~~~~~~~~~~~~~                             //
//                             Module PixelEngine                             //
//                             ~~~~~~~~~~~~~~~~~~                             //
////////////////////////////////////////////////////////////////////////////////

// Register AQDepthConfig.
// ~~~~~~~~~~~~~~~~~~~~~~
#define AQDepthConfigRegAddrs                                             0x0500
#define AQ_DEPTH_CONFIG_Address                                          0x01400
#define AQ_DEPTH_CONFIG_MSB                                                   15
#define AQ_DEPTH_CONFIG_LSB                                                    0
#define AQ_DEPTH_CONFIG_Count                                                  1
#define AQ_DEPTH_CONFIG_FieldMask                                     0xF3333F3B
#define AQ_DEPTH_CONFIG_ReadMask                                      0xF3333F3B
#define AQ_DEPTH_CONFIG_WriteMask                                     0xF3333F3B
#define AQ_DEPTH_CONFIG_ResetValue                                    0x00000000

// Mask bits 30:28.
#define AQ_DEPTH_CONFIG_MASK_INTERLEAVED                                   31:31
#define AQ_DEPTH_CONFIG_MASK_INTERLEAVED_End                                  31
#define AQ_DEPTH_CONFIG_MASK_INTERLEAVED_Start                                31
#define   AQ_DEPTH_CONFIG_MASK_INTERLEAVED_ENABLED                           0x0
#define   AQ_DEPTH_CONFIG_MASK_INTERLEAVED_MASKED                            0x1

// Interleave depth with frame buffer data.
#define AQ_DEPTH_CONFIG_INTERLEAVED                                        30:28
#define AQ_DEPTH_CONFIG_INTERLEAVED_End                                       30
#define AQ_DEPTH_CONFIG_INTERLEAVED_Start                                     28
#define   AQ_DEPTH_CONFIG_INTERLEAVED_DISABLED                               0x0
#define   AQ_DEPTH_CONFIG_INTERLEAVED_C16D16                                 0x1
#define   AQ_DEPTH_CONFIG_INTERLEAVED_C16D32                                 0x2
#define   AQ_DEPTH_CONFIG_INTERLEAVED_C32D16                                 0x3
#define   AQ_DEPTH_CONFIG_INTERLEAVED_C32D32                                 0x4

// Mask bit 24.
#define AQ_DEPTH_CONFIG_MASK_DISABLE_PE_DEPTH                              25:25
#define AQ_DEPTH_CONFIG_MASK_DISABLE_PE_DEPTH_End                             25
#define AQ_DEPTH_CONFIG_MASK_DISABLE_PE_DEPTH_Start                           25
#define   AQ_DEPTH_CONFIG_MASK_DISABLE_PE_DEPTH_ENABLED                      0x0
#define   AQ_DEPTH_CONFIG_MASK_DISABLE_PE_DEPTH_MASKED                       0x1

// Disable PE depth.  This sholud be used when a game is
// pre-pass depth where the depth buffer gets created and a
// seperate rendering pass is done to shade the pixels.  In
// this case, early depth is enabled and the depth copmare is
// set to EQUAL and depth write is disabled.  The driver can
// detect this mode and disable PE depth as well to reduce
// bandwidth requirements.
#define AQ_DEPTH_CONFIG_DISABLE_PE_DEPTH                                   24:24
#define AQ_DEPTH_CONFIG_DISABLE_PE_DEPTH_End                                  24
#define AQ_DEPTH_CONFIG_DISABLE_PE_DEPTH_Start                                24
#define   AQ_DEPTH_CONFIG_DISABLE_PE_DEPTH_ENABLED                           0x0
#define   AQ_DEPTH_CONFIG_DISABLE_PE_DEPTH_DISABLED                          0x1

// Mask bit 20.
#define AQ_DEPTH_CONFIG_MASK_DEPTH_ONLY                                    21:21
#define AQ_DEPTH_CONFIG_MASK_DEPTH_ONLY_End                                   21
#define AQ_DEPTH_CONFIG_MASK_DEPTH_ONLY_Start                                 21
#define   AQ_DEPTH_CONFIG_MASK_DEPTH_ONLY_ENABLED                            0x0
#define   AQ_DEPTH_CONFIG_MASK_DEPTH_ONLY_MASKED                             0x1

// Enable depth-only mode.  In this mode there are no pixels,
// just depth values.  This increases the throughput to one
// depth per cycle.
#define AQ_DEPTH_CONFIG_DEPTH_ONLY                                         20:20
#define AQ_DEPTH_CONFIG_DEPTH_ONLY_End                                        20
#define AQ_DEPTH_CONFIG_DEPTH_ONLY_Start                                      20
#define   AQ_DEPTH_CONFIG_DEPTH_ONLY_DISABLED                                0x0
#define   AQ_DEPTH_CONFIG_DEPTH_ONLY_ENABLED                                 0x1

// Mask bit 16.
#define AQ_DEPTH_CONFIG_MASK_EARLY                                         17:17
#define AQ_DEPTH_CONFIG_MASK_EARLY_End                                        17
#define AQ_DEPTH_CONFIG_MASK_EARLY_Start                                      17
#define   AQ_DEPTH_CONFIG_MASK_EARLY_ENABLED                                 0x0
#define   AQ_DEPTH_CONFIG_MASK_EARLY_MASKED                                  0x1

// Enable early depth comparision in the rasterizer.  Any
// pixel that will be killed by their depth value will not be
// sent down to the Shader.
#define AQ_DEPTH_CONFIG_EARLY                                              16:16
#define AQ_DEPTH_CONFIG_EARLY_End                                             16
#define AQ_DEPTH_CONFIG_EARLY_Start                                           16
#define   AQ_DEPTH_CONFIG_EARLY_DISABLED                                     0x0
#define   AQ_DEPTH_CONFIG_EARLY_ENABLED                                      0x1

// Mask bit 12.
#define AQ_DEPTH_CONFIG_MASK_WRITE                                         13:13
#define AQ_DEPTH_CONFIG_MASK_WRITE_End                                        13
#define AQ_DEPTH_CONFIG_MASK_WRITE_Start                                      13
#define   AQ_DEPTH_CONFIG_MASK_WRITE_ENABLED                                 0x0
#define   AQ_DEPTH_CONFIG_MASK_WRITE_MASKED                                  0x1

// Enable writing of the depth values.
#define AQ_DEPTH_CONFIG_WRITE                                              12:12
#define AQ_DEPTH_CONFIG_WRITE_End                                             12
#define AQ_DEPTH_CONFIG_WRITE_Start                                           12
#define   AQ_DEPTH_CONFIG_WRITE_DISABLED                                     0x0
#define   AQ_DEPTH_CONFIG_WRITE_ENABLED                                      0x1

// Mask bits 10:8.
#define AQ_DEPTH_CONFIG_MASK_COMPARE                                       11:11
#define AQ_DEPTH_CONFIG_MASK_COMPARE_End                                      11
#define AQ_DEPTH_CONFIG_MASK_COMPARE_Start                                    11
#define   AQ_DEPTH_CONFIG_MASK_COMPARE_ENABLED                               0x0
#define   AQ_DEPTH_CONFIG_MASK_COMPARE_MASKED                                0x1

// Compare operation for depth values.  When the copmare
// fails, the pixel will be discarded.
#define AQ_DEPTH_CONFIG_COMPARE                                             10:8
#define AQ_DEPTH_CONFIG_COMPARE_End                                           10
#define AQ_DEPTH_CONFIG_COMPARE_Start                                          8
#define   AQ_DEPTH_CONFIG_COMPARE_NEVER                                      0x0
#define   AQ_DEPTH_CONFIG_COMPARE_LESS                                       0x1
#define   AQ_DEPTH_CONFIG_COMPARE_EQUAL                                      0x2
#define   AQ_DEPTH_CONFIG_COMPARE_LESS_EQUAL                                 0x3
#define   AQ_DEPTH_CONFIG_COMPARE_GREATER                                    0x4
#define   AQ_DEPTH_CONFIG_COMPARE_NOT_EQUAL                                  0x5
#define   AQ_DEPTH_CONFIG_COMPARE_GREATER_EQUAL                              0x6
#define   AQ_DEPTH_CONFIG_COMPARE_ALWAYS                                     0x7

// Mask bit 4.
#define AQ_DEPTH_CONFIG_MASK_FORMAT                                          5:5
#define AQ_DEPTH_CONFIG_MASK_FORMAT_End                                        5
#define AQ_DEPTH_CONFIG_MASK_FORMAT_Start                                      5
#define   AQ_DEPTH_CONFIG_MASK_FORMAT_ENABLED                                0x0
#define   AQ_DEPTH_CONFIG_MASK_FORMAT_MASKED                                 0x1

// Depth format.
#define AQ_DEPTH_CONFIG_FORMAT                                               4:4
#define AQ_DEPTH_CONFIG_FORMAT_End                                             4
#define AQ_DEPTH_CONFIG_FORMAT_Start                                           4
#define   AQ_DEPTH_CONFIG_FORMAT_Z16                                         0x0
#define   AQ_DEPTH_CONFIG_FORMAT_Z24                                         0x1

// Mask bits 1:0.
#define AQ_DEPTH_CONFIG_MASK_TYPE                                            3:3
#define AQ_DEPTH_CONFIG_MASK_TYPE_End                                          3
#define AQ_DEPTH_CONFIG_MASK_TYPE_Start                                        3
#define   AQ_DEPTH_CONFIG_MASK_TYPE_ENABLED                                  0x0
#define   AQ_DEPTH_CONFIG_MASK_TYPE_MASKED                                   0x1

// Depth type (GC500 has W reserved).
#define AQ_DEPTH_CONFIG_TYPE                                                 1:0
#define AQ_DEPTH_CONFIG_TYPE_End                                               1
#define AQ_DEPTH_CONFIG_TYPE_Start                                             0
#define   AQ_DEPTH_CONFIG_TYPE_NONE                                          0x0
#define   AQ_DEPTH_CONFIG_TYPE_Z                                             0x1
#define   AQ_DEPTH_CONFIG_TYPE_W                                             0x2

// Register AQDepthNear.
// ~~~~~~~~~~~~~~~~~~~~
#define AQDepthNearRegAddrs                                               0x0501
#define AQ_DEPTH_NEAR_Address                                            0x01404
#define AQ_DEPTH_NEAR_MSB                                                     15
#define AQ_DEPTH_NEAR_LSB                                                      0
#define AQ_DEPTH_NEAR_Count                                                    1
#define AQ_DEPTH_NEAR_FieldMask                                       0xFFFFFFFF
#define AQ_DEPTH_NEAR_ReadMask                                        0xFFFFFFFF
#define AQ_DEPTH_NEAR_WriteMask                                       0xFFFFFFFF
#define AQ_DEPTH_NEAR_ResetValue                                      0x00000000

// Near value for depth in float.  Since GC500 has no W, this
// should always be 0.0.
#define AQ_DEPTH_NEAR_NEAR                                                  31:0
#define AQ_DEPTH_NEAR_NEAR_End                                                31
#define AQ_DEPTH_NEAR_NEAR_Start                                               0

// Register AQDepthFar.
// ~~~~~~~~~~~~~~~~~~~
#define AQDepthFarRegAddrs                                                0x0502
#define AQ_DEPTH_FAR_Address                                             0x01408
#define AQ_DEPTH_FAR_MSB                                                      15
#define AQ_DEPTH_FAR_LSB                                                       0
#define AQ_DEPTH_FAR_Count                                                     1
#define AQ_DEPTH_FAR_FieldMask                                        0xFFFFFFFF
#define AQ_DEPTH_FAR_ReadMask                                         0xFFFFFFFF
#define AQ_DEPTH_FAR_WriteMask                                        0xFFFFFFFF
#define AQ_DEPTH_FAR_ResetValue                                       0x00000000

// Far value for depth in float.  Since GC500 has no W, this
// should always be 1.0.
#define AQ_DEPTH_FAR_FAR                                                    31:0
#define AQ_DEPTH_FAR_FAR_End                                                  31
#define AQ_DEPTH_FAR_FAR_Start                                                 0

// Register AQDepthNormalize.
// ~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQDepthNormalizeRegAddrs                                          0x0503
#define AQ_DEPTH_NORMALIZE_Address                                       0x0140C
#define AQ_DEPTH_NORMALIZE_MSB                                                15
#define AQ_DEPTH_NORMALIZE_LSB                                                 0
#define AQ_DEPTH_NORMALIZE_Count                                               1
#define AQ_DEPTH_NORMALIZE_FieldMask                                  0xFFFFFFFF
#define AQ_DEPTH_NORMALIZE_ReadMask                                   0xFFFFFFFF
#define AQ_DEPTH_NORMALIZE_WriteMask                                  0xFFFFFFFF
#define AQ_DEPTH_NORMALIZE_ResetValue                                 0x00000000

// Set to MaxDepthValue / (DepthFar - DepthNear).
#define AQ_DEPTH_NORMALIZE_NORMALIZE                                        31:0
#define AQ_DEPTH_NORMALIZE_NORMALIZE_End                                      31
#define AQ_DEPTH_NORMALIZE_NORMALIZE_Start                                     0

// Register AQDepthAddress.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Address of	depth buffer.

#define AQDepthAddressRegAddrs                                            0x0504
#define AQ_DEPTH_ADDRESS_Address                                         0x01410
#define AQ_DEPTH_ADDRESS_MSB                                                  15
#define AQ_DEPTH_ADDRESS_LSB                                                   0
#define AQ_DEPTH_ADDRESS_Count                                                 1
#define AQ_DEPTH_ADDRESS_FieldMask                                    0xFFFFFFFF
#define AQ_DEPTH_ADDRESS_ReadMask                                     0xFFFFFFFC
#define AQ_DEPTH_ADDRESS_WriteMask                                    0xFFFFFFFC
#define AQ_DEPTH_ADDRESS_ResetValue                                   0x00000000

#define AQ_DEPTH_ADDRESS_TYPE                                              31:31
#define AQ_DEPTH_ADDRESS_TYPE_End                                             31
#define AQ_DEPTH_ADDRESS_TYPE_Start                                           31
#define   AQ_DEPTH_ADDRESS_TYPE_SYSTEM                                       0x0
#define   AQ_DEPTH_ADDRESS_TYPE_VIRTUAL_SYSTEM                               0x1

#define AQ_DEPTH_ADDRESS_ADDRESS                                            30:0
#define AQ_DEPTH_ADDRESS_ADDRESS_End                                          30
#define AQ_DEPTH_ADDRESS_ADDRESS_Start                                         0

// Register AQDepthStride.
// ~~~~~~~~~~~~~~~~~~~~~~

// Stride of depth buffer.

#define AQDepthStrideRegAddrs                                             0x0505
#define AQ_DEPTH_STRIDE_Address                                          0x01414
#define AQ_DEPTH_STRIDE_MSB                                                   15
#define AQ_DEPTH_STRIDE_LSB                                                    0
#define AQ_DEPTH_STRIDE_Count                                                  1
#define AQ_DEPTH_STRIDE_FieldMask                                     0x0003FFFF
#define AQ_DEPTH_STRIDE_ReadMask                                      0x0003FFFC
#define AQ_DEPTH_STRIDE_WriteMask                                     0x0003FFFC
#define AQ_DEPTH_STRIDE_ResetValue                                    0x00000000

#define AQ_DEPTH_STRIDE_STRIDE                                              17:0
#define AQ_DEPTH_STRIDE_STRIDE_End                                            17
#define AQ_DEPTH_STRIDE_STRIDE_Start                                           0

// Register AQStencilOperation.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQStencilOperationRegAddrs                                        0x0506
#define AQ_STENCIL_OPERATION_Address                                     0x01418
#define AQ_STENCIL_OPERATION_MSB                                              15
#define AQ_STENCIL_OPERATION_LSB                                               0
#define AQ_STENCIL_OPERATION_Count                                             1
#define AQ_STENCIL_OPERATION_FieldMask                                0xFFFFFFFF
#define AQ_STENCIL_OPERATION_ReadMask                                 0xFFFFFFFF
#define AQ_STENCIL_OPERATION_WriteMask                                0xFFFFFFFF
#define AQ_STENCIL_OPERATION_ResetValue                               0x00000000

// Mask bits 30:28.
#define AQ_STENCIL_OPERATION_MASK_CCW_DEPTH_FAIL                           31:31
#define AQ_STENCIL_OPERATION_MASK_CCW_DEPTH_FAIL_End                          31
#define AQ_STENCIL_OPERATION_MASK_CCW_DEPTH_FAIL_Start                        31
#define   AQ_STENCIL_OPERATION_MASK_CCW_DEPTH_FAIL_ENABLED                   0x0
#define   AQ_STENCIL_OPERATION_MASK_CCW_DEPTH_FAIL_MASKED                    0x1

// Stencil operation for back-faced pixels when the depth
// compare fas failed.
#define AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL                                30:28
#define AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_End                               30
#define AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_Start                             28
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_KEEP                           0x0
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_ZERO                           0x1
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_REPLACE                        0x2
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_INCREMENT_SAT                  0x3
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_DECREMENT_SAT                  0x4
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_INVERT                         0x5
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_INCREMENT                      0x6
#define   AQ_STENCIL_OPERATION_CCW_DEPTH_FAIL_DECREMENT                      0x7

// Mask bits 26:24.
#define AQ_STENCIL_OPERATION_MASK_CCW_FAIL                                 27:27
#define AQ_STENCIL_OPERATION_MASK_CCW_FAIL_End                                27
#define AQ_STENCIL_OPERATION_MASK_CCW_FAIL_Start                              27
#define   AQ_STENCIL_OPERATION_MASK_CCW_FAIL_ENABLED                         0x0
#define   AQ_STENCIL_OPERATION_MASK_CCW_FAIL_MASKED                          0x1

// Stencil operation for back-faced pixels when the depth
// compare has succeeded but the stencil test has failed.
#define AQ_STENCIL_OPERATION_CCW_FAIL                                      26:24
#define AQ_STENCIL_OPERATION_CCW_FAIL_End                                     26
#define AQ_STENCIL_OPERATION_CCW_FAIL_Start                                   24
#define   AQ_STENCIL_OPERATION_CCW_FAIL_KEEP                                 0x0
#define   AQ_STENCIL_OPERATION_CCW_FAIL_ZERO                                 0x1
#define   AQ_STENCIL_OPERATION_CCW_FAIL_REPLACE                              0x2
#define   AQ_STENCIL_OPERATION_CCW_FAIL_INCREMENT_SAT                        0x3
#define   AQ_STENCIL_OPERATION_CCW_FAIL_DECREMENT_SAT                        0x4
#define   AQ_STENCIL_OPERATION_CCW_FAIL_INVERT                               0x5
#define   AQ_STENCIL_OPERATION_CCW_FAIL_INCREMENT                            0x6
#define   AQ_STENCIL_OPERATION_CCW_FAIL_DECREMENT                            0x7

// Mask bits 22:20.
#define AQ_STENCIL_OPERATION_MASK_CCW_PASS                                 23:23
#define AQ_STENCIL_OPERATION_MASK_CCW_PASS_End                                23
#define AQ_STENCIL_OPERATION_MASK_CCW_PASS_Start                              23
#define   AQ_STENCIL_OPERATION_MASK_CCW_PASS_ENABLED                         0x0
#define   AQ_STENCIL_OPERATION_MASK_CCW_PASS_MASKED                          0x1

// Stencil operation for back-faced pixels when the depth
// compare and stencil test have succeeded.
#define AQ_STENCIL_OPERATION_CCW_PASS                                      22:20
#define AQ_STENCIL_OPERATION_CCW_PASS_End                                     22
#define AQ_STENCIL_OPERATION_CCW_PASS_Start                                   20
#define   AQ_STENCIL_OPERATION_CCW_PASS_KEEP                                 0x0
#define   AQ_STENCIL_OPERATION_CCW_PASS_ZERO                                 0x1
#define   AQ_STENCIL_OPERATION_CCW_PASS_REPLACE                              0x2
#define   AQ_STENCIL_OPERATION_CCW_PASS_INCREMENT_SAT                        0x3
#define   AQ_STENCIL_OPERATION_CCW_PASS_DECREMENT_SAT                        0x4
#define   AQ_STENCIL_OPERATION_CCW_PASS_INVERT                               0x5
#define   AQ_STENCIL_OPERATION_CCW_PASS_INCREMENT                            0x6
#define   AQ_STENCIL_OPERATION_CCW_PASS_DECREMENT                            0x7

// Mask bits 18:16.
#define AQ_STENCIL_OPERATION_MASK_CCW_COMPARE                              19:19
#define AQ_STENCIL_OPERATION_MASK_CCW_COMPARE_End                             19
#define AQ_STENCIL_OPERATION_MASK_CCW_COMPARE_Start                           19
#define   AQ_STENCIL_OPERATION_MASK_CCW_COMPARE_ENABLED                      0x0
#define   AQ_STENCIL_OPERATION_MASK_CCW_COMPARE_MASKED                       0x1

// Stencil compare operation for back-faced pixels.
#define AQ_STENCIL_OPERATION_CCW_COMPARE                                   18:16
#define AQ_STENCIL_OPERATION_CCW_COMPARE_End                                  18
#define AQ_STENCIL_OPERATION_CCW_COMPARE_Start                                16
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_NEVER                             0x0
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_LESS                              0x1
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_EQUAL                             0x2
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_LESS_EQUAL                        0x3
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_GREATER                           0x4
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_NOT_EQUAL                         0x5
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_GREATER_EQUAL                     0x6
#define   AQ_STENCIL_OPERATION_CCW_COMPARE_ALWAYS                            0x7

// Mask bits 14:12.
#define AQ_STENCIL_OPERATION_MASK_DEPTH_FAIL                               15:15
#define AQ_STENCIL_OPERATION_MASK_DEPTH_FAIL_End                              15
#define AQ_STENCIL_OPERATION_MASK_DEPTH_FAIL_Start                            15
#define   AQ_STENCIL_OPERATION_MASK_DEPTH_FAIL_ENABLED                       0x0
#define   AQ_STENCIL_OPERATION_MASK_DEPTH_FAIL_MASKED                        0x1

// Stencil operation for front- or single-faced pixels when
// the depth compare fas failed.
#define AQ_STENCIL_OPERATION_DEPTH_FAIL                                    14:12
#define AQ_STENCIL_OPERATION_DEPTH_FAIL_End                                   14
#define AQ_STENCIL_OPERATION_DEPTH_FAIL_Start                                 12
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_KEEP                               0x0
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_ZERO                               0x1
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_REPLACE                            0x2
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_INCREMENT_SAT                      0x3
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_DECREMENT_SAT                      0x4
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_INVERT                             0x5
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_INCREMENT                          0x6
#define   AQ_STENCIL_OPERATION_DEPTH_FAIL_DECREMENT                          0x7

// Mask bits 10:8.
#define AQ_STENCIL_OPERATION_MASK_FAIL                                     11:11
#define AQ_STENCIL_OPERATION_MASK_FAIL_End                                    11
#define AQ_STENCIL_OPERATION_MASK_FAIL_Start                                  11
#define   AQ_STENCIL_OPERATION_MASK_FAIL_ENABLED                             0x0
#define   AQ_STENCIL_OPERATION_MASK_FAIL_MASKED                              0x1

// Stencil operation for front- or single-faced pixels when
// the depth compare has succeeded but the stencil test has
// failed.
#define AQ_STENCIL_OPERATION_FAIL                                           10:8
#define AQ_STENCIL_OPERATION_FAIL_End                                         10
#define AQ_STENCIL_OPERATION_FAIL_Start                                        8
#define   AQ_STENCIL_OPERATION_FAIL_KEEP                                     0x0
#define   AQ_STENCIL_OPERATION_FAIL_ZERO                                     0x1
#define   AQ_STENCIL_OPERATION_FAIL_REPLACE                                  0x2
#define   AQ_STENCIL_OPERATION_FAIL_INCREMENT_SAT                            0x3
#define   AQ_STENCIL_OPERATION_FAIL_DECREMENT_SAT                            0x4
#define   AQ_STENCIL_OPERATION_FAIL_INVERT                                   0x5
#define   AQ_STENCIL_OPERATION_FAIL_INCREMENT                                0x6
#define   AQ_STENCIL_OPERATION_FAIL_DECREMENT                                0x7

// Mask bits 6:4.
#define AQ_STENCIL_OPERATION_MASK_PASS                                       7:7
#define AQ_STENCIL_OPERATION_MASK_PASS_End                                     7
#define AQ_STENCIL_OPERATION_MASK_PASS_Start                                   7
#define   AQ_STENCIL_OPERATION_MASK_PASS_ENABLED                             0x0
#define   AQ_STENCIL_OPERATION_MASK_PASS_MASKED                              0x1

// Stencil operation for front- or single-faced pixels when
// the depth compare and stencil test have succeeded.
#define AQ_STENCIL_OPERATION_PASS                                            6:4
#define AQ_STENCIL_OPERATION_PASS_End                                          6
#define AQ_STENCIL_OPERATION_PASS_Start                                        4
#define   AQ_STENCIL_OPERATION_PASS_KEEP                                     0x0
#define   AQ_STENCIL_OPERATION_PASS_ZERO                                     0x1
#define   AQ_STENCIL_OPERATION_PASS_REPLACE                                  0x2
#define   AQ_STENCIL_OPERATION_PASS_INCREMENT_SAT                            0x3
#define   AQ_STENCIL_OPERATION_PASS_DECREMENT_SAT                            0x4
#define   AQ_STENCIL_OPERATION_PASS_INVERT                                   0x5
#define   AQ_STENCIL_OPERATION_PASS_INCREMENT                                0x6
#define   AQ_STENCIL_OPERATION_PASS_DECREMENT                                0x7

// Mask bits 2:0.
#define AQ_STENCIL_OPERATION_MASK_COMPARE                                    3:3
#define AQ_STENCIL_OPERATION_MASK_COMPARE_End                                  3
#define AQ_STENCIL_OPERATION_MASK_COMPARE_Start                                3
#define   AQ_STENCIL_OPERATION_MASK_COMPARE_ENABLED                          0x0
#define   AQ_STENCIL_OPERATION_MASK_COMPARE_MASKED                           0x1

// Stencil compare operation for front- or single-faced
// pixels.
#define AQ_STENCIL_OPERATION_COMPARE                                         2:0
#define AQ_STENCIL_OPERATION_COMPARE_End                                       2
#define AQ_STENCIL_OPERATION_COMPARE_Start                                     0
#define   AQ_STENCIL_OPERATION_COMPARE_NEVER                                 0x0
#define   AQ_STENCIL_OPERATION_COMPARE_LESS                                  0x1
#define   AQ_STENCIL_OPERATION_COMPARE_EQUAL                                 0x2
#define   AQ_STENCIL_OPERATION_COMPARE_LESS_EQUAL                            0x3
#define   AQ_STENCIL_OPERATION_COMPARE_GREATER                               0x4
#define   AQ_STENCIL_OPERATION_COMPARE_NOT_EQUAL                             0x5
#define   AQ_STENCIL_OPERATION_COMPARE_GREATER_EQUAL                         0x6
#define   AQ_STENCIL_OPERATION_COMPARE_ALWAYS                                0x7

// Register AQStencilConfig.
// ~~~~~~~~~~~~~~~~~~~~~~~~
#define AQStencilConfigRegAddrs                                           0x0507
#define AQ_STENCIL_CONFIG_Address                                        0x0141C
#define AQ_STENCIL_CONFIG_MSB                                                 15
#define AQ_STENCIL_CONFIG_LSB                                                  0
#define AQ_STENCIL_CONFIG_Count                                                1
#define AQ_STENCIL_CONFIG_FieldMask                                   0xFFFFFFF3
#define AQ_STENCIL_CONFIG_ReadMask                                    0xFFFFFFF3
#define AQ_STENCIL_CONFIG_WriteMask                                   0xFFFFFFF3
#define AQ_STENCIL_CONFIG_ResetValue                                  0x00000000

// Mask bits 31:24.
#define AQ_STENCIL_CONFIG_MASK_WRITE_MASK                                    7:7
#define AQ_STENCIL_CONFIG_MASK_WRITE_MASK_End                                  7
#define AQ_STENCIL_CONFIG_MASK_WRITE_MASK_Start                                7
#define   AQ_STENCIL_CONFIG_MASK_WRITE_MASK_ENABLED                          0x0
#define   AQ_STENCIL_CONFIG_MASK_WRITE_MASK_MASKED                           0x1

// Stencil write enable bits.
#define AQ_STENCIL_CONFIG_WRITE_MASK                                       31:24
#define AQ_STENCIL_CONFIG_WRITE_MASK_End                                      31
#define AQ_STENCIL_CONFIG_WRITE_MASK_Start                                    24

// Mask bits 23:16.
#define AQ_STENCIL_CONFIG_MASK_MASK                                          6:6
#define AQ_STENCIL_CONFIG_MASK_MASK_End                                        6
#define AQ_STENCIL_CONFIG_MASK_MASK_Start                                      6
#define   AQ_STENCIL_CONFIG_MASK_MASK_ENABLED                                0x0
#define   AQ_STENCIL_CONFIG_MASK_MASK_MASKED                                 0x1

// Stencil mask applied when stencils are read and compared.
#define AQ_STENCIL_CONFIG_MASK                                             23:16
#define AQ_STENCIL_CONFIG_MASK_End                                            23
#define AQ_STENCIL_CONFIG_MASK_Start                                          16

// Mask bits 15:8.
#define AQ_STENCIL_CONFIG_MASK_REFERENCE                                     5:5
#define AQ_STENCIL_CONFIG_MASK_REFERENCE_End                                   5
#define AQ_STENCIL_CONFIG_MASK_REFERENCE_Start                                 5
#define   AQ_STENCIL_CONFIG_MASK_REFERENCE_ENABLED                           0x0
#define   AQ_STENCIL_CONFIG_MASK_REFERENCE_MASKED                            0x1

// Stencil reference value to use for comparison.
#define AQ_STENCIL_CONFIG_REFERENCE                                         15:8
#define AQ_STENCIL_CONFIG_REFERENCE_End                                       15
#define AQ_STENCIL_CONFIG_REFERENCE_Start                                      8

// Mask bits 1:0.
#define AQ_STENCIL_CONFIG_MASK_TYPE                                          4:4
#define AQ_STENCIL_CONFIG_MASK_TYPE_End                                        4
#define AQ_STENCIL_CONFIG_MASK_TYPE_Start                                      4
#define   AQ_STENCIL_CONFIG_MASK_TYPE_ENABLED                                0x0
#define   AQ_STENCIL_CONFIG_MASK_TYPE_MASKED                                 0x1

// Stencil mode.
#define AQ_STENCIL_CONFIG_TYPE                                               1:0
#define AQ_STENCIL_CONFIG_TYPE_End                                             1
#define AQ_STENCIL_CONFIG_TYPE_Start                                           0
#define   AQ_STENCIL_CONFIG_TYPE_NONE                                        0x0
#define   AQ_STENCIL_CONFIG_TYPE_ENABLED                                     0x1
#define   AQ_STENCIL_CONFIG_TYPE_TWO_SIDED                                   0x2

// Register AQAlphaTest.
// ~~~~~~~~~~~~~~~~~~~~
#define AQAlphaTestRegAddrs                                               0x0508
#define AQ_ALPHA_TEST_Address                                            0x01420
#define AQ_ALPHA_TEST_MSB                                                     15
#define AQ_ALPHA_TEST_LSB                                                      0
#define AQ_ALPHA_TEST_Count                                                    1
#define AQ_ALPHA_TEST_FieldMask                                       0x0001FFF3
#define AQ_ALPHA_TEST_ReadMask                                        0x0001FFF3
#define AQ_ALPHA_TEST_WriteMask                                       0x0001FFF3
#define AQ_ALPHA_TEST_ResetValue                                      0x00000000

// Mask bits 15:8.
#define AQ_ALPHA_TEST_MASK_REFERENCE                                       16:16
#define AQ_ALPHA_TEST_MASK_REFERENCE_End                                      16
#define AQ_ALPHA_TEST_MASK_REFERENCE_Start                                    16
#define   AQ_ALPHA_TEST_MASK_REFERENCE_ENABLED                               0x0
#define   AQ_ALPHA_TEST_MASK_REFERENCE_MASKED                                0x1

// Reference value to be used for the alpha test.
#define AQ_ALPHA_TEST_REFERENCE                                             15:8
#define AQ_ALPHA_TEST_REFERENCE_End                                           15
#define AQ_ALPHA_TEST_REFERENCE_Start                                          8

// Mask bits 6:4.
#define AQ_ALPHA_TEST_MASK_COMPARE                                           7:7
#define AQ_ALPHA_TEST_MASK_COMPARE_End                                         7
#define AQ_ALPHA_TEST_MASK_COMPARE_Start                                       7
#define   AQ_ALPHA_TEST_MASK_COMPARE_ENABLED                                 0x0
#define   AQ_ALPHA_TEST_MASK_COMPARE_MASKED                                  0x1

// Compare operation to be used for alpha test.
#define AQ_ALPHA_TEST_COMPARE                                                6:4
#define AQ_ALPHA_TEST_COMPARE_End                                              6
#define AQ_ALPHA_TEST_COMPARE_Start                                            4
#define   AQ_ALPHA_TEST_COMPARE_NEVER                                        0x0
#define   AQ_ALPHA_TEST_COMPARE_LESS                                         0x1
#define   AQ_ALPHA_TEST_COMPARE_EQUAL                                        0x2
#define   AQ_ALPHA_TEST_COMPARE_LESS_EQUAL                                   0x3
#define   AQ_ALPHA_TEST_COMPARE_GREATER                                      0x4
#define   AQ_ALPHA_TEST_COMPARE_NOT_EQUAL                                    0x5
#define   AQ_ALPHA_TEST_COMPARE_GREATER_EQUAL                                0x6
#define   AQ_ALPHA_TEST_COMPARE_ALWAYS                                       0x7

// Mask bit 0.
#define AQ_ALPHA_TEST_MASK_TEST                                              1:1
#define AQ_ALPHA_TEST_MASK_TEST_End                                            1
#define AQ_ALPHA_TEST_MASK_TEST_Start                                          1
#define   AQ_ALPHA_TEST_MASK_TEST_ENABLED                                    0x0
#define   AQ_ALPHA_TEST_MASK_TEST_MASKED                                     0x1

// Enable alpha test.  If the alpha test is enabled and
// fails, the	pixel is discarded.
#define AQ_ALPHA_TEST_TEST                                                   0:0
#define AQ_ALPHA_TEST_TEST_End                                                 0
#define AQ_ALPHA_TEST_TEST_Start                                               0
#define   AQ_ALPHA_TEST_TEST_DISABLED                                        0x0
#define   AQ_ALPHA_TEST_TEST_ENABLED                                         0x1

// Register AQAlphaBlendFactor.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQAlphaBlendFactorRegAddrs                                        0x0509
#define AQ_ALPHA_BLEND_FACTOR_Address                                    0x01424
#define AQ_ALPHA_BLEND_FACTOR_MSB                                             15
#define AQ_ALPHA_BLEND_FACTOR_LSB                                              0
#define AQ_ALPHA_BLEND_FACTOR_Count                                            1
#define AQ_ALPHA_BLEND_FACTOR_FieldMask                               0xFFFFFFFF
#define AQ_ALPHA_BLEND_FACTOR_ReadMask                                0xFFFFFFFF
#define AQ_ALPHA_BLEND_FACTOR_WriteMask                               0xFFFFFFFF
#define AQ_ALPHA_BLEND_FACTOR_ResetValue                              0x00000000

// Alpha blend factor for the alpha channel.
#define AQ_ALPHA_BLEND_FACTOR_ALPHA                                        31:24
#define AQ_ALPHA_BLEND_FACTOR_ALPHA_End                                       31
#define AQ_ALPHA_BLEND_FACTOR_ALPHA_Start                                     24

// Alpha blend factor for the red channel.
#define AQ_ALPHA_BLEND_FACTOR_RED                                          23:16
#define AQ_ALPHA_BLEND_FACTOR_RED_End                                         23
#define AQ_ALPHA_BLEND_FACTOR_RED_Start                                       16

// Alpha blend factor for the green channel.
#define AQ_ALPHA_BLEND_FACTOR_GREEN                                         15:8
#define AQ_ALPHA_BLEND_FACTOR_GREEN_End                                       15
#define AQ_ALPHA_BLEND_FACTOR_GREEN_Start                                      8

// Alpha blend factor for the blue channel.
#define AQ_ALPHA_BLEND_FACTOR_BLUE                                           7:0
#define AQ_ALPHA_BLEND_FACTOR_BLUE_End                                         7
#define AQ_ALPHA_BLEND_FACTOR_BLUE_Start                                       0

// Register AQAlphaBlend.
// ~~~~~~~~~~~~~~~~~~~~~
#define AQAlphaBlendRegAddrs                                              0x050A
#define AQ_ALPHA_BLEND_Address                                           0x01428
#define AQ_ALPHA_BLEND_MSB                                                    15
#define AQ_ALPHA_BLEND_LSB                                                     0
#define AQ_ALPHA_BLEND_Count                                                   1
#define AQ_ALPHA_BLEND_FieldMask                                      0xFFFFFFFF
#define AQ_ALPHA_BLEND_ReadMask                                       0xFFFFFFFF
#define AQ_ALPHA_BLEND_WriteMask                                      0xFFFFFFFF
#define AQ_ALPHA_BLEND_ResetValue                                     0x00000000

// Mask bits 30:28.
#define AQ_ALPHA_BLEND_MASK_OPERATION_ALPHA                                31:31
#define AQ_ALPHA_BLEND_MASK_OPERATION_ALPHA_End                               31
#define AQ_ALPHA_BLEND_MASK_OPERATION_ALPHA_Start                             31
#define   AQ_ALPHA_BLEND_MASK_OPERATION_ALPHA_ENABLED                        0x0
#define   AQ_ALPHA_BLEND_MASK_OPERATION_ALPHA_MASKED                         0x1

// Operation between source and destination alpha channels.
#define AQ_ALPHA_BLEND_OPERATION_ALPHA                                     30:28
#define AQ_ALPHA_BLEND_OPERATION_ALPHA_End                                    30
#define AQ_ALPHA_BLEND_OPERATION_ALPHA_Start                                  28
#define   AQ_ALPHA_BLEND_OPERATION_ALPHA_ADD                                 0x0
#define   AQ_ALPHA_BLEND_OPERATION_ALPHA_SUBTRACT                            0x1
#define   AQ_ALPHA_BLEND_OPERATION_ALPHA_REVERSE_SUBTRACT                    0x2
#define   AQ_ALPHA_BLEND_OPERATION_ALPHA_MIN                                 0x3
#define   AQ_ALPHA_BLEND_OPERATION_ALPHA_MAX                                 0x4

// Mask bits 27:24.
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND_ALPHA                               19:19
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND_ALPHA_End                              19
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND_ALPHA_Start                            19
#define   AQ_ALPHA_BLEND_MASK_DEST_BLEND_ALPHA_ENABLED                       0x0
#define   AQ_ALPHA_BLEND_MASK_DEST_BLEND_ALPHA_MASKED                        0x1

// Selection for destination alpha channel.
#define AQ_ALPHA_BLEND_DEST_BLEND_ALPHA                                    27:24
#define AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_End                                   27
#define AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_Start                                 24
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_ZERO                               0x0
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_ONE                                0x1
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_SRC_COLOR                          0x2
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_SRC_COLOR                      0x3
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_SRC_ALPHA                          0x4
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_SRC_ALPHA                      0x5
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_DEST_ALPHA                         0x6
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_DEST_ALPHA                     0x7
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_DEST_COLOR                         0x8
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_DEST_COLOR                     0x9
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_SRC_ALPHA_SAT                      0xA
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_BLEND_FACTOR_ALPHA                 0xB
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_BLEND_FACTOR_ALPHA             0xC
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_BLEND_FACTOR                       0xD
#define   AQ_ALPHA_BLEND_DEST_BLEND_ALPHA_INV_BLEND_FACTOR                   0xE

// Mask bits 23:20.
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND_ALPHA                                18:18
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND_ALPHA_End                               18
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND_ALPHA_Start                             18
#define   AQ_ALPHA_BLEND_MASK_SRC_BLEND_ALPHA_ENABLED                        0x0
#define   AQ_ALPHA_BLEND_MASK_SRC_BLEND_ALPHA_MASKED                         0x1

// Selection for source alpha channel.
#define AQ_ALPHA_BLEND_SRC_BLEND_ALPHA                                     23:20
#define AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_End                                    23
#define AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_Start                                  20
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_ZERO                                0x0
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_ONE                                 0x1
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_SRC_COLOR                           0x2
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_SRC_COLOR                       0x3
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_SRC_ALPHA                           0x4
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_SRC_ALPHA                       0x5
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_DEST_ALPHA                          0x6
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_DEST_ALPHA                      0x7
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_DEST_COLOR                          0x8
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_DEST_COLOR                      0x9
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_SRC_ALPHA_SAT                       0xA
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_BLEND_FACTOR_ALPHA                  0xB
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_BLEND_FACTOR_ALPHA              0xC
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_BLEND_FACTOR                        0xD
#define   AQ_ALPHA_BLEND_SRC_BLEND_ALPHA_INV_BLEND_FACTOR                    0xE

// Mask bit 16.
#define AQ_ALPHA_BLEND_MASK_ENABLE_ALPHA                                   17:17
#define AQ_ALPHA_BLEND_MASK_ENABLE_ALPHA_End                                  17
#define AQ_ALPHA_BLEND_MASK_ENABLE_ALPHA_Start                                17
#define   AQ_ALPHA_BLEND_MASK_ENABLE_ALPHA_ENABLED                           0x0
#define   AQ_ALPHA_BLEND_MASK_ENABLE_ALPHA_MASKED                            0x1

// Enable seperate alpha channel source selection.  If
// disabled, the alpha channel blending will the same as the
// color channel blending.
#define AQ_ALPHA_BLEND_ENABLE_ALPHA                                        16:16
#define AQ_ALPHA_BLEND_ENABLE_ALPHA_End                                       16
#define AQ_ALPHA_BLEND_ENABLE_ALPHA_Start                                     16
#define   AQ_ALPHA_BLEND_ENABLE_ALPHA_DISABLED                               0x0
#define   AQ_ALPHA_BLEND_ENABLE_ALPHA_ENABLED                                0x1

// Mask bits 14:12.
#define AQ_ALPHA_BLEND_MASK_OPERATION                                      15:15
#define AQ_ALPHA_BLEND_MASK_OPERATION_End                                     15
#define AQ_ALPHA_BLEND_MASK_OPERATION_Start                                   15
#define   AQ_ALPHA_BLEND_MASK_OPERATION_ENABLED                              0x0
#define   AQ_ALPHA_BLEND_MASK_OPERATION_MASKED                               0x1

// Operation between source and destination color channels.
#define AQ_ALPHA_BLEND_OPERATION                                           14:12
#define AQ_ALPHA_BLEND_OPERATION_End                                          14
#define AQ_ALPHA_BLEND_OPERATION_Start                                        12
#define   AQ_ALPHA_BLEND_OPERATION_ADD                                       0x0
#define   AQ_ALPHA_BLEND_OPERATION_SUBTRACT                                  0x1
#define   AQ_ALPHA_BLEND_OPERATION_REVERSE_SUBTRACT                          0x2
#define   AQ_ALPHA_BLEND_OPERATION_MIN                                       0x3
#define   AQ_ALPHA_BLEND_OPERATION_MAX                                       0x4

// Mask bits 11:8.
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND                                       3:3
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND_End                                     3
#define AQ_ALPHA_BLEND_MASK_DEST_BLEND_Start                                   3
#define   AQ_ALPHA_BLEND_MASK_DEST_BLEND_ENABLED                             0x0
#define   AQ_ALPHA_BLEND_MASK_DEST_BLEND_MASKED                              0x1

// Selection for destination color channels.
#define AQ_ALPHA_BLEND_DEST_BLEND                                           11:8
#define AQ_ALPHA_BLEND_DEST_BLEND_End                                         11
#define AQ_ALPHA_BLEND_DEST_BLEND_Start                                        8
#define   AQ_ALPHA_BLEND_DEST_BLEND_ZERO                                     0x0
#define   AQ_ALPHA_BLEND_DEST_BLEND_ONE                                      0x1
#define   AQ_ALPHA_BLEND_DEST_BLEND_SRC_COLOR                                0x2
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_SRC_COLOR                            0x3
#define   AQ_ALPHA_BLEND_DEST_BLEND_SRC_ALPHA                                0x4
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_SRC_ALPHA                            0x5
#define   AQ_ALPHA_BLEND_DEST_BLEND_DEST_ALPHA                               0x6
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_DEST_ALPHA                           0x7
#define   AQ_ALPHA_BLEND_DEST_BLEND_DEST_COLOR                               0x8
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_DEST_COLOR                           0x9
#define   AQ_ALPHA_BLEND_DEST_BLEND_SRC_ALPHA_SAT                            0xA
#define   AQ_ALPHA_BLEND_DEST_BLEND_BLEND_FACTOR_ALPHA                       0xB
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_BLEND_FACTOR_ALPHA                   0xC
#define   AQ_ALPHA_BLEND_DEST_BLEND_BLEND_FACTOR                             0xD
#define   AQ_ALPHA_BLEND_DEST_BLEND_INV_BLEND_FACTOR                         0xE

// Mask bits 7:4.
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND                                        2:2
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND_End                                      2
#define AQ_ALPHA_BLEND_MASK_SRC_BLEND_Start                                    2
#define   AQ_ALPHA_BLEND_MASK_SRC_BLEND_ENABLED                              0x0
#define   AQ_ALPHA_BLEND_MASK_SRC_BLEND_MASKED                               0x1

// Selection for source color channels.
#define AQ_ALPHA_BLEND_SRC_BLEND                                             7:4
#define AQ_ALPHA_BLEND_SRC_BLEND_End                                           7
#define AQ_ALPHA_BLEND_SRC_BLEND_Start                                         4
#define   AQ_ALPHA_BLEND_SRC_BLEND_ZERO                                      0x0
#define   AQ_ALPHA_BLEND_SRC_BLEND_ONE                                       0x1
#define   AQ_ALPHA_BLEND_SRC_BLEND_SRC_COLOR                                 0x2
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_SRC_COLOR                             0x3
#define   AQ_ALPHA_BLEND_SRC_BLEND_SRC_ALPHA                                 0x4
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_SRC_ALPHA                             0x5
#define   AQ_ALPHA_BLEND_SRC_BLEND_DEST_ALPHA                                0x6
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_DEST_ALPHA                            0x7
#define   AQ_ALPHA_BLEND_SRC_BLEND_DEST_COLOR                                0x8
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_DEST_COLOR                            0x9
#define   AQ_ALPHA_BLEND_SRC_BLEND_SRC_ALPHA_SAT                             0xA
#define   AQ_ALPHA_BLEND_SRC_BLEND_BLEND_FACTOR_ALPHA                        0xB
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_BLEND_FACTOR_ALPHA                    0xC
#define   AQ_ALPHA_BLEND_SRC_BLEND_BLEND_FACTOR                              0xD
#define   AQ_ALPHA_BLEND_SRC_BLEND_INV_BLEND_FACTOR                          0xE

// Mask bit 0.
#define AQ_ALPHA_BLEND_MASK_ENABLE                                           1:1
#define AQ_ALPHA_BLEND_MASK_ENABLE_End                                         1
#define AQ_ALPHA_BLEND_MASK_ENABLE_Start                                       1
#define   AQ_ALPHA_BLEND_MASK_ENABLE_ENABLED                                 0x0
#define   AQ_ALPHA_BLEND_MASK_ENABLE_MASKED                                  0x1

// Enable alpha blending.
#define AQ_ALPHA_BLEND_ENABLE                                                0:0
#define AQ_ALPHA_BLEND_ENABLE_End                                              0
#define AQ_ALPHA_BLEND_ENABLE_Start                                            0
#define   AQ_ALPHA_BLEND_ENABLE_DISABLED                                     0x0
#define   AQ_ALPHA_BLEND_ENABLE_ENABLED                                      0x1

// Register AQPixelConfig.
// ~~~~~~~~~~~~~~~~~~~~~~
#define AQPixelConfigRegAddrs                                             0x050B
#define AQ_PIXEL_CONFIG_Address                                          0x0142C
#define AQ_PIXEL_CONFIG_MSB                                                   15
#define AQ_PIXEL_CONFIG_LSB                                                    0
#define AQ_PIXEL_CONFIG_Count                                                  1
#define AQ_PIXEL_CONFIG_FieldMask                                     0x00001F1F
#define AQ_PIXEL_CONFIG_ReadMask                                      0x00001F1F
#define AQ_PIXEL_CONFIG_WriteMask                                     0x00001F1F
#define AQ_PIXEL_CONFIG_ResetValue                                    0x00000000

// Mask bits 11:8.
#define AQ_PIXEL_CONFIG_MASK_COLOR_WRITE                                   12:12
#define AQ_PIXEL_CONFIG_MASK_COLOR_WRITE_End                                  12
#define AQ_PIXEL_CONFIG_MASK_COLOR_WRITE_Start                                12
#define   AQ_PIXEL_CONFIG_MASK_COLOR_WRITE_ENABLED                           0x0
#define   AQ_PIXEL_CONFIG_MASK_COLOR_WRITE_MASKED                            0x1

// Each bit represents an enable bit for its specific
// channel.
#define AQ_PIXEL_CONFIG_COLOR_WRITE                                         11:8
#define AQ_PIXEL_CONFIG_COLOR_WRITE_End                                       11
#define AQ_PIXEL_CONFIG_COLOR_WRITE_Start                                      8
#define   AQ_PIXEL_CONFIG_COLOR_WRITE_RED                                    0x1
#define   AQ_PIXEL_CONFIG_COLOR_WRITE_GREEN                                  0x2
#define   AQ_PIXEL_CONFIG_COLOR_WRITE_BLUE                                   0x4
#define   AQ_PIXEL_CONFIG_COLOR_WRITE_ALPHA                                  0x8

// Mask bits 3:0.
#define AQ_PIXEL_CONFIG_MASK_FORMAT                                          4:4
#define AQ_PIXEL_CONFIG_MASK_FORMAT_End                                        4
#define AQ_PIXEL_CONFIG_MASK_FORMAT_Start                                      4
#define   AQ_PIXEL_CONFIG_MASK_FORMAT_ENABLED                                0x0
#define   AQ_PIXEL_CONFIG_MASK_FORMAT_MASKED                                 0x1

// Render target format.
#define AQ_PIXEL_CONFIG_FORMAT                                               3:0
#define AQ_PIXEL_CONFIG_FORMAT_End                                             3
#define AQ_PIXEL_CONFIG_FORMAT_Start                                           0
#define   AQ_PIXEL_CONFIG_FORMAT_X4R4G4B4                                    0x0
#define   AQ_PIXEL_CONFIG_FORMAT_A4R4G4B4                                    0x1
#define   AQ_PIXEL_CONFIG_FORMAT_X1R5G5B5                                    0x2
#define   AQ_PIXEL_CONFIG_FORMAT_A1R5G5B5                                    0x3
#define   AQ_PIXEL_CONFIG_FORMAT_R5G6B5                                      0x4
#define   AQ_PIXEL_CONFIG_FORMAT_X8R8G8B8                                    0x5
#define   AQ_PIXEL_CONFIG_FORMAT_A8R8G8B8                                    0x6
#define   AQ_PIXEL_CONFIG_FORMAT_YUY2                                        0x7
#define   AQ_PIXEL_CONFIG_FORMAT_UYVY                                        0x8
#define   AQ_PIXEL_CONFIG_FORMAT_INDEX8                                      0x9
#define   AQ_PIXEL_CONFIG_FORMAT_MONOCHROME                                  0xA
#define   AQ_PIXEL_CONFIG_FORMAT_HDR7E3                                      0xB
#define   AQ_PIXEL_CONFIG_FORMAT_HDR6E4                                      0xC
#define   AQ_PIXEL_CONFIG_FORMAT_HDR5E5                                      0xD
#define   AQ_PIXEL_CONFIG_FORMAT_HDR6E5                                      0xE
#define   AQ_PIXEL_CONFIG_FORMAT_YV12                                        0xF

// Register AQPixelAddress.
// ~~~~~~~~~~~~~~~~~~~~~~~

// Address of the render target.

#define AQPixelAddressRegAddrs                                            0x050C
#define AQ_PIXEL_ADDRESS_Address                                         0x01430
#define AQ_PIXEL_ADDRESS_MSB                                                  15
#define AQ_PIXEL_ADDRESS_LSB                                                   0
#define AQ_PIXEL_ADDRESS_Count                                                 1
#define AQ_PIXEL_ADDRESS_FieldMask                                    0xFFFFFFFF
#define AQ_PIXEL_ADDRESS_ReadMask                                     0xFFFFFFFC
#define AQ_PIXEL_ADDRESS_WriteMask                                    0xFFFFFFFC
#define AQ_PIXEL_ADDRESS_ResetValue                                   0x00000000

#define AQ_PIXEL_ADDRESS_TYPE                                              31:31
#define AQ_PIXEL_ADDRESS_TYPE_End                                             31
#define AQ_PIXEL_ADDRESS_TYPE_Start                                           31
#define   AQ_PIXEL_ADDRESS_TYPE_SYSTEM                                       0x0
#define   AQ_PIXEL_ADDRESS_TYPE_VIRTUAL_SYSTEM                               0x1

#define AQ_PIXEL_ADDRESS_ADDRESS                                            30:0
#define AQ_PIXEL_ADDRESS_ADDRESS_End                                          30
#define AQ_PIXEL_ADDRESS_ADDRESS_Start                                         0

// Register AQPixelStride.
// ~~~~~~~~~~~~~~~~~~~~~~

// Stride of the render target.

#define AQPixelStrideRegAddrs                                             0x050D
#define AQ_PIXEL_STRIDE_Address                                          0x01434
#define AQ_PIXEL_STRIDE_MSB                                                   15
#define AQ_PIXEL_STRIDE_LSB                                                    0
#define AQ_PIXEL_STRIDE_Count                                                  1
#define AQ_PIXEL_STRIDE_FieldMask                                     0x0003FFFF
#define AQ_PIXEL_STRIDE_ReadMask                                      0x0003FFFC
#define AQ_PIXEL_STRIDE_WriteMask                                     0x0003FFFC
#define AQ_PIXEL_STRIDE_ResetValue                                    0x00000000

#define AQ_PIXEL_STRIDE_STRIDE                                              17:0
#define AQ_PIXEL_STRIDE_STRIDE_End                                            17
#define AQ_PIXEL_STRIDE_STRIDE_Start                                           0

// Register AQPEBistControl.
// ~~~~~~~~~~~~~~~~~~~~~~~~
#define AQPEBistControlRegAddrs                                           0x050E
#define AQPE_BIST_CONTROL_Address                                        0x01438
#define AQPE_BIST_CONTROL_MSB                                                 15
#define AQPE_BIST_CONTROL_LSB                                                  0
#define AQPE_BIST_CONTROL_Count                                                1
#define AQPE_BIST_CONTROL_FieldMask                                   0x00000003
#define AQPE_BIST_CONTROL_ReadMask                                    0x00000003
#define AQPE_BIST_CONTROL_WriteMask                                   0x00000003
#define AQPE_BIST_CONTROL_ResetValue                                  0x00000000

#define AQPE_BIST_CONTROL_RESET                                              0:0
#define AQPE_BIST_CONTROL_RESET_End                                            0
#define AQPE_BIST_CONTROL_RESET_Start                                          0
#define   AQPE_BIST_CONTROL_RESET_NOT_RESET                                  0x0
#define   AQPE_BIST_CONTROL_RESET_RESET                                      0x1

#define AQPE_BIST_CONTROL_MODE                                               1:1
#define AQPE_BIST_CONTROL_MODE_End                                             1
#define AQPE_BIST_CONTROL_MODE_Start                                           1
#define   AQPE_BIST_CONTROL_MODE_NOT_BIST_MODE                               0x0
#define   AQPE_BIST_CONTROL_MODE_BIST_MODE                                   0x1

// Register AQPEBistStatus0.
// ~~~~~~~~~~~~~~~~~~~~~~~~
#define AQPEBistStatus0RegAddrs                                           0x050F
#define AQPE_BIST_STATUS0_Address                                        0x0143C
#define AQPE_BIST_STATUS0_MSB                                                 15
#define AQPE_BIST_STATUS0_LSB                                                  0
#define AQPE_BIST_STATUS0_Count                                                1
#define AQPE_BIST_STATUS0_FieldMask                                   0x00000001
#define AQPE_BIST_STATUS0_ReadMask                                    0x00000001
#define AQPE_BIST_STATUS0_WriteMask                                   0x00000001
#define AQPE_BIST_STATUS0_ResetValue                                  0x00000000

#define AQPE_BIST_STATUS0_DONE                                               0:0
#define AQPE_BIST_STATUS0_DONE_End                                             0
#define AQPE_BIST_STATUS0_DONE_Start                                           0
#define   AQPE_BIST_STATUS0_DONE_NOT_DONE                                    0x0
#define   AQPE_BIST_STATUS0_DONE_DONE                                        0x1

// Register AQPEBistStatus1.
// ~~~~~~~~~~~~~~~~~~~~~~~~
#define AQPEBistStatus1RegAddrs                                           0x0510
#define AQPE_BIST_STATUS1_Address                                        0x01440
#define AQPE_BIST_STATUS1_MSB                                                 15
#define AQPE_BIST_STATUS1_LSB                                                  0
#define AQPE_BIST_STATUS1_Count                                                1
#define AQPE_BIST_STATUS1_FieldMask                                   0x000FFFFF
#define AQPE_BIST_STATUS1_ReadMask                                    0x000FFFFF
#define AQPE_BIST_STATUS1_WriteMask                                   0x000FFFFF
#define AQPE_BIST_STATUS1_ResetValue                                  0x00000000

#define AQPE_BIST_STATUS1_BM_ERROR                                          19:0
#define AQPE_BIST_STATUS1_BM_ERROR_End                                        19
#define AQPE_BIST_STATUS1_BM_ERROR_Start                                       0

// Register AQPixelOpenVG.
// ~~~~~~~~~~~~~~~~~~~~~~
#define AQPixelOpenVGRegAddrs                                             0x0511
#define AQ_PIXEL_OPEN_VG_Address                                         0x01444
#define AQ_PIXEL_OPEN_VG_MSB                                                  15
#define AQ_PIXEL_OPEN_VG_LSB                                                   0
#define AQ_PIXEL_OPEN_VG_Count                                                 1
#define AQ_PIXEL_OPEN_VG_FieldMask                                    0x0000001E
#define AQ_PIXEL_OPEN_VG_ReadMask                                     0x0000001E
#define AQ_PIXEL_OPEN_VG_WriteMask                                    0x0000001E
#define AQ_PIXEL_OPEN_VG_ResetValue                                   0x00000000

#define AQ_PIXEL_OPEN_VG_DST_IN_COLOR_TIME_ALPHA                             1:1
#define AQ_PIXEL_OPEN_VG_DST_IN_COLOR_TIME_ALPHA_End                           1
#define AQ_PIXEL_OPEN_VG_DST_IN_COLOR_TIME_ALPHA_Start                         1
#define   AQ_PIXEL_OPEN_VG_DST_IN_COLOR_TIME_ALPHA_DISABLE                   0x0
#define   AQ_PIXEL_OPEN_VG_DST_IN_COLOR_TIME_ALPHA_ENABLE                    0x1

#define AQ_PIXEL_OPEN_VG_DST_OUT_COLOR_DIVIDE_ALPHA                          2:2
#define AQ_PIXEL_OPEN_VG_DST_OUT_COLOR_DIVIDE_ALPHA_End                        2
#define AQ_PIXEL_OPEN_VG_DST_OUT_COLOR_DIVIDE_ALPHA_Start                      2
#define   AQ_PIXEL_OPEN_VG_DST_OUT_COLOR_DIVIDE_ALPHA_DISABLE                0x0
#define   AQ_PIXEL_OPEN_VG_DST_OUT_COLOR_DIVIDE_ALPHA_ENABLE                 0x1

#define AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM                                    4:3
#define AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_End                                  4
#define AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_Start                                3
#define   AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_DISABLE                          0x0
#define   AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_SRC_TIME_DST                     0x1
#define   AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_MIN_ALPHA_COLOR_CROSS            0x2
#define   AQ_PIXEL_OPEN_VG_THIRD_COLOR_TERM_MAX_ALPHA_COLOR_CROSS            0x3

// Register AQPixelCacheDebug.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQPixelCacheDebugRegAddrs                                         0x0512
#define AQ_PIXEL_CACHE_DEBUG_Address                                     0x01448
#define AQ_PIXEL_CACHE_DEBUG_MSB                                              15
#define AQ_PIXEL_CACHE_DEBUG_LSB                                               0
#define AQ_PIXEL_CACHE_DEBUG_Count                                             1
#define AQ_PIXEL_CACHE_DEBUG_FieldMask                                0x0000000F
#define AQ_PIXEL_CACHE_DEBUG_ReadMask                                 0x0000000F
#define AQ_PIXEL_CACHE_DEBUG_WriteMask                                0x0000000F
#define AQ_PIXEL_CACHE_DEBUG_ResetValue                               0x0000000D

#define AQ_PIXEL_CACHE_DEBUG_MAX_WRITE_OUT                                   3:0
#define AQ_PIXEL_CACHE_DEBUG_MAX_WRITE_OUT_End                                 3
#define AQ_PIXEL_CACHE_DEBUG_MAX_WRITE_OUT_Start                               0

// Register AQPixelMcMaskCtrl.
// ~~~~~~~~~~~~~~~~~~~~~~~~~~
#define AQPixelMcMaskCtrlRegAddrs                                         0x0513
#define AQ_PIXEL_MC_MASK_CTRL_Address                                    0x0144C
#define AQ_PIXEL_MC_MASK_CTRL_MSB                                             15
#define AQ_PIXEL_MC_MASK_CTRL_LSB                                              0
#define AQ_PIXEL_MC_MASK_CTRL_Count                                            1
#define AQ_PIXEL_MC_MASK_CTRL_FieldMask                               0x00000001
#define AQ_PIXEL_MC_MASK_CTRL_ReadMask                                0x00000001
#define AQ_PIXEL_MC_MASK_CTRL_WriteMask                               0x00000001
#define AQ_PIXEL_MC_MASK_CTRL_ResetValue                              0x00000000

#define AQ_PIXEL_MC_MASK_CTRL_MC_MASK_DISABLE                                0:0
#define AQ_PIXEL_MC_MASK_CTRL_MC_MASK_DISABLE_End                              0
#define AQ_PIXEL_MC_MASK_CTRL_MC_MASK_DISABLE_Start                            0

